DRAM (dynamic random access memory) modules are fabricated in increasingly large volumes, for a wide variety of computer applications. As computer processing capabilities continue to improve, recent generation DRAM modules are required to have an ever-increasing storage density, to thereby achieve smaller dimensions while containing a larger number of memory cells for storing data. This results in a need to further reduce the cell size of individual memory cells, comprised of a storage capacitance and a selection transistor. Depending upon the arrangement of the storage capacitance, e.g., in the silicon substrate or below the transistors used for driving purposes or above the substrate surface or above the transistors, a distinction is made between memory cells of a “trench capacitor” type and of a “stacked capacitor” type.
In the case of a memory cell of the “trench capacitor” type, a trench is formed in a monocrystalline semiconductor substrate, with a capacitor being introduced into the trench step-by-step. By means of outdiffusion, for example, a doped region is first formed in regions of the semiconductor substrate that adjoin the trench wall. The regions form a first outer electrode in the completed capacitor. A thin layer of a dielectric, such as a nitride/oxide layer, is then deposited along the trench wall. A second, inner electrode may subsequently be formed as a counterelectrode by deposition of highly doped polycrystalline silicon in the remaining cavity of the trench. Afterward, in the region of the semiconductor substrate near the surface and above the capacitor, a transistor and associated interconnects are produced, which can be used to control the charge state of the capacitor.
In a memory cell of the “stacked capacitor” type, the control electronics, including a selection transistor and interconnects for driving the memory cell, are first constructed in or on a monocrystalline semiconductor substrate. Afterward, a dielectric layer may be applied, such as on the semiconductor substrate surface, having a thickness that corresponds at least to the extent of the capacitor in the direction perpendicular to the surface of the semiconductor substrate. A cavity in the form of a trench is then introduced into said dielectric layer, said cavity reaching as far as the previously constructed control electronics or the corresponding connections. In a manner comparable with the fabrication of a trench capacitor, a capacitor is subsequently constructed by step-by-step deposition of outer electrode, dielectric and inner electrode in the cavity.
The fabrication of a stacked capacitor as explained here is to be regarded only as by way of example. There are a multiplicity of different concepts for a stacked capacitor, which, however, are based on common features. The transistor controlling the charge state of the stacked capacitor is arranged below the stacked capacitor, in contrast to the trench capacitor. Both trench capacitor and stacked capacitor thus follows similar principles in terms of their construction. Both use an extent perpendicular to the surface of the semiconductor substrate and achieve an enlargement of the electrode area by virtue of the capacitor being as it were “folded”.
Reducing the cell size leads to capacitors having a smaller cross section, for which reason the area of the electrodes also decreases, which ultimately leads to capacitors having a lower electrical capacitance. In order to compensate for the loss of capacitance, it is necessary to increase the capacitance again in a different way by means of complicated new process techniques. Examples thereof are capacitors with a higher doping of the electrodes in order to reduce the charge carrier depletion or the use of dielectrics having a high dielectric constant. The surfaces of the electrodes can be enlarged, for example, by applying additional structures (HSG, hemispherical grains) on the trench wall.
A further possibility for increasing the capacitance consists, in the case of trench capacitors, in enlarging the surface of the trench by means of a bottle-like extension in a lower section of the trench. The trench thus extends in the depth of the semiconductor substrate also partially into regions of the semiconductor substrate which are located below a selection transistor formed on the surface of the semiconductor substrate.
Stacked capacitors manifest in principle the same difficulties when reducing the cross section of the capacitor. In this case, too, the electrode area and thus the capacitance of the capacitor decrease as the cross section decreases.
Given feature sizes of less than a hundred nanometers, the capacitance of the capacitors which are currently used in commercial microchips, for a predetermined cross section, can be increased by the abovementioned methods only by a value which is typically below 50%. In order to satisfy the requirements made of future chip generations, however, a far greater increase in the capacitance is necessary, or, to put it another way, a capacitance remaining approximately the same per memory cell has to be made available as the feature size of the capacitors which are integrated in a microchip decreases.